There are many ways to solve EMI problems. Modern EMI suppression methods include EMI suppression coating, EMI suppression parts and EMI simulation design, etc. Starting from the most basic PCB layout, this paper discusses the role and design skills of PCB layering and stacking in controlling EMI radiation.
Power busbar
The jump of IC output voltage can be made faster by placing a capacitor of appropriate capacity near the IC power pin. However, the problem does not end there. Due to the limited frequency response of the capacitor, it is not possible to generate the harmonic power needed to drive IC output cleanly in the full frequency band. In addition, the transient voltage generated on the power bus-bar forms a voltage drop at both ends of the inductance of the decoupling path, and these transient voltages are the main common mode EMI interference sources. How should we solve these problems?
In the case of the IC on our circuit board, the power layer around the IC can be regarded as a good high-frequency capacitor, which can collect the leakage of energy from discrete capacitors that provide high-frequency energy for clean output. In addition, the inductance of a good power layer is small, which leads to the synthesis of transient signals and reduces common mode EMI.
Of course, the connection between the power layer and the IC power pin must be as short as possible, because the digital signal rises faster and faster, it is better to connect directly to the welding pad where the IC power pin is located, which is discussed separately.
To control common mode EMI, the power layer must be a well-designed pair of power layers to help with decoupling and inductance low enough. One might ask, how good is good? The answer depends on the layers of the power supply, the materials between the layers, and the operating frequency (which is a function of the rise time of the IC). In general, the spacing of the power supply layers is 6mil and the sandwich is FR4 material, so the equivalent capacitance of the power supply layer per square inch is about 75pF. Obviously, the smaller the spacing, the larger the capacitance.
Not many devices have a rise time of 100 to 300ps, but at the current rate of IC development, devices with a rise time of 100 to 300ps will account for a high proportion. For circuits with a rise time of 100 to 300ps, the 3mil layer spacing is no longer applicable for most applications. At that time, it is necessary to adopt layer spacing less than 1mil and replace FR4 dielectric material with material with high dielectric constant. Now, ceramic and ceramic plastics can meet the design requirements of 100 to 300ps rise-time circuits.
Although new materials and methods may be used in the future, the 1 to 3ns rise-time circuits, 3 to 6mil interlayer spacing, and FR4 dielectric materials common today are usually sufficient to handle the high-end harmonics and keep the transient signal low enough, that is, the common mode EMI can fall very low. The PCB layer-stack design example presented in this paper will assume layer spacing of 3 to 6mil.
Electromagnetic shielding
In terms of signal wiring, a good layering strategy would be to place all signal wiring in one or more layers next to the power supply or ground plane. For power supply, a good stratification strategy should be that the power supply layer is adjacent to the grounding layer, and the distance between the power supply layer and the grounding layer should be as small as possible. This is what we call the “stratification” strategy.
PCB stack
What stack strategies help block and suppress EMI? The following layered stacking scheme assumes that the supply current flows over a single layer, with single or multiple voltages distributed over different parts of the same layer. The case of multiple power layers is discussed later.
4 layer board
There are several potential problems in the design of laminate. First of all, the conventional four-layer plate with a thickness of 62mil is too large even though the signal layer is in the outer layer and the power layer and the grounding layer are in the inner layer.
If the cost requirement is the first priority, we can consider the following two traditional 4-layer board alternatives. Both schemes improve EMI suppression, but only when the element density on the board is low enough and the area around the element is large enough (to place the required copper-clad power supply).
The first is the preferred solution. The outer layer of PCB is stratigraphic, and the middle two layers are signal/power layer. The power supply on the signal layer is wired with wide lines, which makes the path impedance of the power supply current low and the path impedance of the signal microstrip low. From the point of view of EMI control, this is the best 4 layer PCB structure available. The second scheme of the outer power and ground, the middle two layers of signal. Compared with traditional 4-layer laminates, this scheme has a smaller improvement, and the inter-layer impedance is as poor as that of traditional 4-layer laminates.
If wiring resistance is to be controlled, the stacking scheme above must be carefully positioned below the power supply and ground copper island. In addition, the power supply or copper-laying islands on the ground should be interlinked as much as possible to ensure DC and low frequency connectivity.
6 layer board
If the element density on 4 laminates is relatively large, it is better to use 6 laminates. However, some of the layering schemes in the 6-layer panel design do not shield electromagnetic fields well enough, and have little effect on reducing the transient signal of the power bus bar. Two examples are discussed below.
In the first case, the power source and the ground were placed in layer 2 and layer 5 respectively. Due to the high copper-clad impedance of the power source, it was very unfavorable to control common mode EMI radiation. However, from the point of view of signal impedance control, this approach is quite correct.
In the second example, the power source and ground are placed in layer 3 and layer 4 respectively. This design solves the problem of copper-clad impedance of the power source. Due to the poor electromagnetic shielding performance of layer 1 and layer 6, the difference mode EMI increases. This design can solve the differential mode EMI problem if the number of signal lines on the two outer layers is minimal and the wiring length is very short (less than 1/20 of the signal’s highest harmonic wavelength). Copper-filled and copper-coated areas on the outer layer (with intervals of 1/20 wavelength) are particularly good at suppressing differential mode EMI. As mentioned above, the copper-laying area should be connected to multiple points of the inner ground layer.
The general high performance 6 layer board design generally includes layers 1 and 6 for the stratum, 3 and 4 for the power supply and ground. As there are two layers of double microstrip signal lines between the power supply layer and the grounding layer, EMI suppression ability is excellent. The disadvantage of this design is that there are only two layers of wiring. As mentioned earlier, if the outer wiring is short and copper is laid in the area without wiring, the same stacking can be achieved with traditional 6-layer boards.
The other 6-layer layout is signal, ground, signal, power, ground, signal, which enables the environment needed for advanced signal integrity design. The signal layer is adjacent to the grounding layer, and the power layer is paired with the grounding layer. Obviously, the drawback is that the layers are stacked out of balance.
This usually leads to manufacturing problems. The solution is to fill all the gaps in the third layer with copper. If the copper coating density of the third layer is close to that of the power layer or the ground layer, the board can be loosely counted as a structurally balanced circuit board. The copper filling area must be connected to power or grounded. The distance between connecting holes is still 1/20 wavelength, not necessarily everywhere, but ideally it should be.
10 layer board
Because the insulation between layers is very thin, the impedance between 10 or 12 layers of circuit boards is very low, and excellent signal integrity is expected as long as there are no problems with layering and stacking. It is difficult to manufacture 12 laminates according to the thickness of 62mil, and few manufacturers can process 12 laminates.
Since there is always an insulating layer between the signal layer and the loop layer, it is not optimal to allocate the middle six layers in the 10-layer board design to route the signal line. In addition, it is very important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.
This design provides a good path for signal current and its loop current. The appropriate wiring strategy is for layer 1 to line in the X direction, layer 3 to line in the Y direction, layer 4 to line in the X direction, and so on. Intuitively speaking, layers 1 and 3 are a pair of layers, layers 4 and 7 are a pair of layers, and layers 8 and 10 are the last pair of layers. When it is necessary to change the direction of the line, the signal line on the first layer should go through the “hole” to the third layer before changing the direction. In fact, this may not always be possible, but as a design concept, try to stick to it.
Similarly, when the direction of the signal is changed, the signal should pass through the hole from the 8th and 10th layers or from the 4th to the 7th layers. This wiring ensures maximum coupling between the forward path of the signal and the circuit. For example, if the signal is wired on layer 1, and the circuit is wired on layer 2 and only on layer 2, then the signal on layer 1 is still wired on layer 2, even if it is transferred to layer 3 through the “hole”, thus maintaining the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.
What if the actual route is not like this? For example, if the signal wire on the first layer goes through the hole to the 10th layer, then the circuit signal has to find the grounding plane from the 9th layer, and the circuit current has to find the nearest grounding hole (such as the grounding pin of a resistor or capacitor). If you happen to have one nearby, you’re in luck. If no such near hole is available, the inductance will be larger, the capacitance will be reduced, and EMI will certainly increase.
When the signal line must leave the current pair of wiring layers to other wiring layers through the holes, the grounding holes should be placed close to the holes, so that the circuit signal can return to the appropriate grounding layer smoothly. For layer 4 and layer 7 layering combinations, the signal loop will return from the power layer or ground layer (i.e., layer 5 or layer 6), since the capacitive coupling between the power layer and ground layer is good and the signal is easy to transmit.
Multi-power layer design
If two power layers of the same voltage source need to output large current, the circuit board should be arranged into two power layers and grounding layers. In this case, an insulating layer is placed between each pair of power layers and the grounding layer. This gives us the desired supply bus-bar with two equal impedance pairs that divide the current equally. If the stack of the power layers results in unequal impedance, the shunt will be uneven, the transient voltage will be much higher, and the EMI will increase sharply.
If there are multiple numerically different power supply voltages on the circuit board, multiple power supply layers are required, keeping in mind that a pair of power supply layers and grounding layers are created for the different power sources. In both cases, determine where the paired power layer and grounding layer are located on the circuit board, bearing in mind the manufacturer’s requirements for balanced construction.
conclusion
Since most of the circuit boards designed by engineers are traditional printed circuit boards with a thickness of 62mil and without blind or buried holes, the discussion of layering and stacking of circuit boards in this paper is limited to this point. If the thickness difference of circuit board is too great, the layering scheme recommended in this paper may not be ideal. In addition, the layering method is not suitable for blind hole or buried hole PCB.
In circuit board design, thickness, through hole process and number of layers of circuit board are not the key to solve the problem. Excellent layering and stacking are the key to ensure the bypass and decoupling of power bus, minimize the transient voltage on the power layer or ground, and shield the electromagnetic field of signal and power. Ideally, there should be an insulating layer between the signal routing layer and the loop grounding layer, and the spacing of paired layers (or more than one pair) should be as small as possible. According to these basic concepts and principles, can be designed to always meet the design requirements of the circuit board. Now that the rise time of IC has been very short and will be even shorter, the techniques discussed in this paper are essential for solving EMI shielding problems.