As a PCB design engineer, it is necessary to have certain high-speed knowledge. In terms of signals, high-speed signals usually appear in various parallel buses and serial buses. Only when we know what is the bus can we know its running speed and start wiring.

A bus is a shared physical path for communication between two or more devices, a collection of signal lines, and a common connection between multiple components, used to transfer information between various components. The bus can be divided into two types: parallel bus and serial bus.


Parallel bus

Multiple data can be transmitted at the same time, such as a spacious road that allows multiple vehicles to run in parallel, and it has the difference between two-way and one-way.


Serial bus

At the same time, only one data can be transmitted, such as a narrow road, and only one car is allowed to walk. Data must be transmitted one by one, which looks like a long data string, so it is called “serial”.
The best example of “parallel transmission” is the memory chip DDR, which has a set of data lines d0-d7, DQS and DQM. This set of lines is transmitted together. No matter which bit is wrong, the past data cannot be transmitted correctly, only retransmitted. Therefore, each data line must be the same length and must be wound several times.

Serial data is different. Data is transmitted bit by bit, and there is no connection between bits. It will not prevent the next person from transmitting due to this error. Parallel data is a set of data, one of which is wrong, and the entire set of data is incorrect.

Wiring requirements


Parallel bus wiring requirements

(1) It is recommended to optimize the inner-layer wiring of the bus, and increase the distance between the bus and other wiring as much as possible.

(2) Except for special requirements, the single-line design impedance is guaranteed to be 50Ω, and the differential design impedance is guaranteed to be 100Ω.

(3) It is recommended that the same group of buses maintain the same basic wiring length, follow a certain timing relationship with the clock line, and analyze the wiring length with reference to the timing.

(4) It is recommended to be as close as possible to the I / O power or GND reference plane of this group of buses to ensure the integrity of the reference plane.

(5) For passenger cars with a rise time less than 1ns, a complete datum is required, and crossing and division are not allowed.

(6) It is recommended that the low address bus reference clock wiring requirements.

(7) The pitch of the serpentine line should not be less than 3 times the line width.

High-speed serial bus wiring requirements

For a serial bus with a frequency higher than 100Mbps, in addition to following the general crosstalk control and parallel bus wiring rules, some additional requirements should be considered in the wiring design:

(1) The high-speed serial bus needs to consider the line loss and determine the line width and length.

(2) It is recommended that the width of the downstream line is not less than 5MIL, and the wiring is as short as possible.

(3) Except for fan-shaped holes, the high-speed serial bus should not be perforated due to layer changes.

(4) When the pin speed of the plug-in involved in the serial bus is greater than 3.125gbps, the solder pad should be optimized to reduce the effect of impedance discontinuity.

(5) It is recommended to select the wiring layer with the least through-hole stubs when replacing the wiring layer of the high-speed serial bus. For the signal to the connector, when the wiring space is limited, the short-circuit layer with short vias should be assigned to the transmitter first.

(6) When the speed reaches 3.125gbps or above, it is recommended to drill a ground hole next to the signal through hole, and the reverse pad should also specially deal with AC coupling capacitors.

(7) When using the reverse drilling method to process high-speed signal vias, it is necessary to consider the effects of reduced power ground plane flow and increased filter loop inductance after the overcurrent bottleneck narrows.

(8) The high-speed signal avoids the dividing line of the Kaiping surface layer, ensuring that the horizontal distance between the edge of the signal line and the dividing line is 3W.

(9) Send and receive high-speed signals from two directions. These two directions cannot cross and route together.