Emi problems in printed circuit boards include common impedance coupling, crosstalk, radiation from high-frequency current-carrying wires, and induction of printed lines to high-frequency radiation. The following describes the PCB design in order to meet the electromagnetic compatibility must pay attention to matters.

1. The common impedance coupling problems in PCB for analog and digital circuit respectively have their own pathway, power supply and ground where possible, should be widened as far as possible this two part of the circuit of power from the power source of the ground or use separate layer and ground layer, in order to reduce the power and the impedance of the ground loop, reduce any possible interference voltage in power supply and ground. The analog and digital ground of a single working PCB can be connected at a single point near the connection point of the system. If the power supply voltage is consistent, the power supply of the analog and digital circuit can be connected at a single point at the power supply inlet. If the PCB is plugged into the motherboard, the power supply and ground of the analog and digital circuits of the motherboard shall also be separated. The analog ground and digital ground shall be grounded at the connection of the motherboard, and the power supply processing shall be the same as above.

2. PCB layout design requirements are summarized as follows: • when high-speed, medium-speed and low-speed digital circuits are mixed, they are assigned different layout areas on the printed board. • separate low level analog and digital logic circuits as much as possible. Figure 1 is the optimal layout for a printed board. Because of this arrangement, the routing path of high-frequency current on the PCB can be shortened, which helps to reduce the crosstalk, common impedance coupling and radiation emission within the PCB. Figure 2 shows an analog circuit on a circuit board. Separate analog and digital circuits; As for the logic circuit on the circuit board, the similar layout as shown in figure 1 is used, that is, high-speed logic circuit should be as close as possible to the edge of the circuit board. Figure 1: digital circuit board layout figure 2: digital and analog circuits mixed with the layout

Multilayer PCB design

3.1 in the electromagnetic compatibility design of digital circuits, the bandwidth determined by the rising and falling edges of digital pulses rather than the repetition frequency of digital pulses should be considered. A square digital signal board is designed with a bandwidth of 1 / PI tr, usually ten times the frequency of that bandwidth being considered.

3.2 the number of layers of multilayer PCB should be determined in the design of multilayer PCB. The arrangement between layers of a multilayer PCB varies with the circuit, but there are several common principles.

(1) the power supply plane shall be close to the ground plane and arranged below the ground plane. In this way, the capacitance between the two metal plates can be used as the smooth capacitance of the power supply, and the grounding plane can also shield the radiation current distributed on the power supply plane.

(2) wiring layer shall be arranged adjacent to the whole metal plane. This arrangement is designed to produce a flux cancellation.

(3) separate digital circuit and analog circuit, and arrange digital circuit and analog circuit in different layers when possible. If you must arrange in the same layer; Can use the method such as furrow, add ground line, space to remedy. Analog and digital ground, power are separated, can not be mixed. Digital signals have a wide spectrum and are the main source of interference.

(4) the printed lines in the middle layer form plane waveguides and microstrip lines are formed on the surface, with different transmission characteristics.

(5) clock circuit and high-frequency circuit are the main sources of interference and radiation, must be arranged separately, away from the sensitive circuit.

(6) the stray current and high-frequency radiation current contained in different layers are different and cannot be regarded as the same when wiring. 3.3 typical layering arrangement of multilayer PCB: 1, 2, 3, 4, 5, 6, 7, 8, 9, 102 layers S1,G, 7, 8, 9, 6 layers S1,G, S2, 6 layers S1,G, S2, S3,P, S4 6 layers S1, S2, G, S3,P, S4 6 layers S1, S2, G, S3,P, S4 8 layers S1, S2, G, S3,P, S4 8 layers S1,G, S2, G, S3,P, S4 8 layers S1,G, S2, G, S3,G, S4 S3 G P S4, S5 G S63.4 two basic principles in multilayer PCB design, there are two basic principles to determine the printing line spacing and margins: 20 – H principle all have certain voltage of PCB to space radiation, electromagnetic energy to reduce this effect, the physical size of the PCB should be smaller than the most close to meet the physical size of the floor 20 H, H is the two PCB surface spacing. According to the general typical PCB size, 20H is generally about 3mm. Principle 2-w when the distance between two printed lines is small, electromagnetic crosstalk will occur between the two lines, crosstalk will make the circuit function abnormal. To avoid such interference, keep any line spacing no less than twice the printed line width, i.e., no less than 2W, where W is the width of the printed line. The width of the printed line depends on the impedance of the line. Large and small size can affect the waveform and strength of the signal transmitted to the terminal. 3.5.1 the concept of distributed parameters shall be established. Above a certain frequency, any metal wire shall be regarded as a device composed of resistance and inductance. Therefore, the grounding leads have a certain impedance and constitute the electrical circuit, whether it is single-point grounding or multi-point grounding, must constitute a low impedance circuit into the real ground or frame. A typical 25mm printed wire would represent an inductance of about 15nH to 20nH, and the presence of distributed capacitance would create a resonant circuit between the ground plate and the rack. 3.5.2 the main transmission line effect and antenna effect will occur when the grounding current flows through the ground wire. When the length of the line is 1/4 wavelength, it can show high impedance. The grounding line is actually open, while the grounding line becomes a dead line radiating outward. 3.5.3 the ground plate is filled with vortices formed by high-frequency currents and interference fields. As a result, a number of loops shall be formed between ground points with diameters (or spacing between ground points) less than 1/20 of the wavelength of the highest frequency. See figure 3.

4 other wiring requirements • dedicated zero volt line and VCC wire width should be 1mm. • provide a dedicated zero volt line for the analog circuit. • the power cord and ground wire of one or two panels should be as close as possible. The best way is to place the power cord on one side of the PCB and the ground wire on the other side of the PCB, with the top and bottom overlapping. This will minimize the impedance of the power supply. In addition, the power supply and ground wire of the entire printed circuit board should be distributed in a “well” character, so that the current of the wiring can be balanced. • special attention should also be paid to the size of the wire loops through which the current flows in the printed circuit design, as these loops are equivalent to small antennas at work, radiating into space wherever and whenever possible. In particular, pay attention to the wiring of the clock part, because this part is the highest working frequency in the whole circuit. • signal routing (especially high frequency signals) should be as short as possible as they are typical transmitting antennas; • crystal oscillator should be as close as possible to IC, and the wiring should be thicker; • grounding of crystal oscillator shell; • the line width on the PCB board should not be abrupt, and the wire should not be suddenly turned. • increase the distance between printed lines if necessary to reduce crosstalk in parallel runs; Or in the line between the conscious placement of a zero volt line, as a line between the isolation; • the power pins of each IC shall be added with bypass capacitance (generally 104) and smooth capacitance (10uF~100uF) to the large area of IC, and the power pins of each corner shall also be added with bypass capacitance and smooth capacitance. • if possible, add RC low-pass filter or EMI suppression element (such as magnetic bead, signal filter, etc.) at the interface of PCB board to eliminate the interference of connection line; But be careful not to interfere with the transmission of useful signals; • the signal interface of the PCB board should allocate as many zero volt line connections as possible and evenly separate the signal lines.

When designing PCB, it is often necessary to add capacitors on the circuit to meet the requirement of power supply stability and cleanliness in digital circuit operation. The capacitors in the circuit can be divided into decoupling capacitors, bypass capacitors and capacitors. Decoupling capacitors are used to filter the radiated current caused by the high-frequency devices on the power supply plate, provide a localized dc for the devices, and reduce the peak current shock in the printed circuit. Bypass capacitors can eliminate high-frequency radiated noise. Noise can limit the bandwidth of the circuit and produce the main common mode interference. Smoothing or holding capacitance is used to solve the problem that the power supply voltage will drop suddenly when the switching device is working. The most important part of the design is to determine the location of the capacitance and the access capacitance. The self – resonant frequency of capacitor is the key parameter of capacitor design. If the capacitor has a lead wire, it will attach inherent inductance and resistance to the capacitor. Considering these factors, the actual capacitor can be regarded as a series resonance circuit composed of resistance, inductance and capacitance, as shown in figure 5. Therefore, the actual capacitors all have self-resonant frequencies, below which the capacitors are capacitive. When the frequency is higher than the auto-resonance frequency, the capacitor is inductive, and the impedance increases with the increase of frequency, so the bypass effect is greatly reduced. The resonant frequency shall be the capacitor with high resonant frequency. Typical ceramic capacitor leads are about 6mm long and inductance of 15nH is introduced. The corresponding self-resonant frequency of this type of capacitor is listed in the table below.

Table 2: capacitor from the resonance frequency of the capacitor of capacitance value (uF) 1 since the resonant frequency of 0.1 0.01 0.001 capacitor (2.5 5 MHz) consisting of 15 50 power between the plate and the floor plate capacitor also has from the resonance frequency, the resonance frequency if and clock frequency if and clock frequency resonance, will make the whole PCB a electromagnetic radiation. This resonant frequency can reach 200MHz ~ 400MHz, and can be increased by 2-3 times by adopting 20-h principle. Using a large-capacity capacitor in parallel with a capacitors of a lower capacity can effectively improve the self-resonance frequency characteristics. When the large-capacity capacitor reaches the resonance point, the impedance of the large-capacity capacitor starts to increase with the increase of frequency. Capacitors with a small capacity have not yet reached the resonance point, but still become smaller as the frequency increases and will dominate the bypass current. The capacitance of the decoupling capacitor is calculated according to the formula, in which “I” stands for transient current, “V” stands for the change of the allowable power supply voltage value of the logic device, and “t” stands for the switching time. When the power lead is long and the transient current causes a large voltage drop, the capacitance must be added to maintain the required voltage value of the device. When designing, first calculate the allowable impedance Zm, Zm= train V/ train I then, from the line inductance Lw to calculate the corresponding frequency FM =Zm/(2 Lw), when using frequency higher than FM, to accommodate the capacitance Cb, usually Cb 10 ~ 100uF between value. Cb = 1 / (2 PI FM Zm) capacitor material is temperature sensitive and must have a good temperature coefficient. Also select equivalent series inductance and capacitor equivalent series resistance is small, general requirements equivalent series inductance value is less than 10 nh, equivalent series resistance is less than 0.5 Ω. Smooth capacitors should be added at every two LSI or VLSI components, and smooth capacitors should be added at the power supply inlet. In addition, the I/O connector, the place far away from the power input connector, the place where the components are dense, and the vicinity of the clock generator circuit should be added with smoothing capacitor. The calculation method of smoothing capacitor is the same as that of decoupling capacitor.

EMC design of clock circuits clock circuits play an important role in digital circuits, and clock circuits are the main source of electromagnetic radiation. A clock signal with 2ns rising edge has a bandwidth of 160MHz radiation energy, and its possible radiation bandwidth is up to 10x frequency, namely 1.6ghz. Therefore, the design of a good clock circuit is the key to ensure that the whole machine radiation index. The main problems of clock circuit design are as follows.

(1) impedance control: calculate the wave impedance, phase shift constant and attenuation constant of various microstrip lines and microstrip waveguides composed of PCB lines. The wave impedance and attenuation constant of some typical structures can be found in many design manuals. The parameters of special microstrip lines and microstrip waveguides need to be solved by computational electromagnetics.

(2) transmission delay and impedance matching: the phase shift constant of the printed line is used to calculate the delay of the clock pulse. When the delay reaches a certain value, impedance matching should be carried out to avoid the clock signal jitter or overshoot caused by terminal reflection. Impedance matching methods include series resistance, parallel resistance, davenin network, RC network, diode array, etc.

(3) the effect of more capacitive loads on printed lines: the capacitive loads on printed lines have a greater impact on the wave impedance of the lines. In particular, the effect on the capacitive load of the bus structure is often a key factor to be considered. The transmission line can be expressed in three ways: a, the transmission wave impedance (Z0) and the transmission delay (td) are used to describe the transmission line.

B. Describe the transmission line in terms of transmitted wave impedance and (in relation to the wavelength) normalized length.

C. Describe transmission lines in terms of inductors, capacitors per unit length and physical length of printed lines. In PCB design, the first method is often used to describe the transmission line composed of printed lines. At this point, the size of the transmission delay determines whether printed lines need to take impedance control measures; When there is a lot of capacitive load on the line, the transmission delay of the line will increase, which is related to the original transmission delay as follows: td ‘is the line transmission delay without considering the capacitive load, C0 is the distributed capacitance of the line without considering the capacitive load, lm is the maximum printed line length without matching. There are many other clock circuit design problems, such as the isolation of the clock zone from other functional zones, the shielding of the clock lines in the same laminate, and so on. Electromagnetic compatibility design skills for clock circuits

(A) proper wiring shall be carried out first and the wiring layer shall be arranged adjacent to the entire metal plane. This arrangement is designed to produce a flux cancellation.

(B) secondly, clock circuits and high-frequency circuits are the main sources of interference and radiation and must be arranged separately from sensitive circuits.

(C) the selection of appropriate devices is an important factor for the success of the design. In particular, when selecting logic devices, try to choose devices whose rise time is longer than five nanoseconds, and never choose logic devices whose timing is faster than that required by the circuit.

(D) the inter-layer jumper should be at least as shown in FIG. 3 and FIG. 4, respectively. FIG. 3 shows the inter-layer jumper arrangement of good and relatively good clock wiring. The scenario shown in figure 4 is not allowed.

Figure 3: interlayer jumper arrangement for better clock wiring

Figure 4: layer jumper arrangement for clock cabling not allowed

When the clock wiring is output through the connector, the pins on the connector should be covered with grounding pins around the clock wiring pins, as shown in figure 5. Figure 5: arrangement of clock wire pins on connectors (F) do not use direct serial connection to multiple parts (called Daisy connection) when clock output wiring; Instead, the clock signal should be directly provided to multiple other parts through the cache.

The use of logic circuits the advice for logic integrated circuits used in circuit design is: • do not use high-speed logic circuits where you can do without them. • note the addition of a by-pass decoupling capacitor (typically 104) between the power supply near the IC and the ground. • pay attention to waveform distortion during long line transmission. • use r-s triggers as a buffer between the device control buttons and the device electronic circuitry.

Within the equipment, improper wiring is the primary cause of interference, most of the interference is between cables in the same cable harness. Therefore, correct wiring is one of the basic guarantees for reliable operation of equipment.

8.1 suppression method of electromagnetic coupling between lines: magnetic coupling: 1) reduce the area of the interference source and the loop of the sensitive circuit. The best way to do this is to use twisted and shielded wires that twist the signal line to the ground (or current-carrying circuit) so that the signal is closest to the ground (or current-carrying circuit). 2) increase the distance between lines, so that the mutual inductance between the interference source and the induced line is as small as possible. 3) if possible, make the circuit of the interference source and the inducted circuit at a right Angle (or close to a right Angle), which can greatly reduce the coupling between the two lines of the capacitive coupling: 1) increase the distance between the lines is the best way to reduce the capacitive coupling. 2) use shielding layer, which should be grounded. 3) reduce the input impedance of sensitive circuit. This is more effective for CMOS circuit, because the input impedance of CMOS circuit is very high, and after voltage separation with electrostatic capacitance, the interference signal is added to the input terminal of CMOS circuit with very high composition. If possible, parallel a capacitor or a low resistance at the population end of a CMOS circuit to the ground, which reduces the input impedance of the circuit and thus reduces the interference introduced by the electrostatic capacitance. 4) if possible, the sensitive circuit USES balance circuit as input, and the balance circuit is ungrounded. In this way, the interference source exerts common mode interference on the population of balanced circuit, which can overcome the interference of interference source on sensitive circuit by utilizing the inherent common mode suppression ability of balanced circuit. 8.2 general wiring methods before formal wiring, the first point is to classify the lines. The main classification method is carried out according to the power level, with each 30dB power level divided into several groups, as shown in the following table: According to the wiring method for classification of power level hierarchical power range features A > 40 DBM high power dc, ac and radio frequency source (EMI) B 10 ~ 40 DBM low power dc, ac and radio frequency source (EMI source) C – 20 ~ 10 DBM pulse and origin, video output circuit (audio video source) D – 50 ~ 20 DBM sensitive sensor circuit, video and audio input circuit sensitive circuits (video) E – 80-50 DBM radio frequency, intermediate frequency output circuit, protection circuit (rf) sensitive circuits F < – 80 DBM The advantages of this classification of antennas and radio frequency circuits are: • both interference sources and receiving circuits are classified by power. • within the same harness, the power level difference between adjacent conductors does not exceed 30dB. Wires of different types should be bundled separately and laid separately. The conductors of adjacent classes may be grouped together after shielding or twisting. The minimum distance between the wiring harnesses laid by classification is 50~75mm.