For capacitance installation, the first thing to mention is the installation distance. The capacitance with the smallest capacitance has the highest resonant frequency and the decoupling radius is the smallest, so it is placed closest to the chip. The larger ones can be a little bit further away, and the outermost ones have the largest volume. However, all capacitors decoupling the chip are as close to the chip as possible.
When placed, it is best to distribute evenly around the chip for each tolerance level. Generally, the chip is designed with the arrangement of power supply and ground pins in mind, and it is generally evenly distributed on the four edges of the chip. Therefore, voltage perturbation exists all around the chip, and decoupling must be uniform to the whole chip region. If the 680pF capacitance in the figure above is placed on the upper part of the chip, the voltage disturbance on the lower part of the chip cannot be well decoupled due to the decoupling radius problem.
When installing capacitors, pull a small lead wire from the solder pad and connect it to the power supply plane through a hole, as well as the grounding end. In this way, the current circuit flowing through the capacitor is as follows: power supply plane – > through hole – > lead out line – > solder pad – > capacitor – > solder pad – > lead out line – > through hole – > ground plane, and figure 2 intuitively shows the reflux path of current.
The first method is to draw a long lead wire from the solder pad and then connect it through the hole, which will introduce a large parasitic inductance, be sure to avoid doing so, this is the worst way to install.
The second method is to punch holes in the two ends of the welding plate next to the welding plate, which is much smaller than the first method and has a smaller parasitic inductance, which is acceptable.
The third is to drill holes on the side of the welding plate, further reducing the loop area, and the parasitic inductance is smaller than the second one, which is a better method.
The fourth is to punch holes on both sides of the welding plate. Compared with the third method, each end of the capacitance is connected to the power supply plane and ground plane in parallel through the hole, which is smaller than the third parasitic inductance. As long as space permits, try to use this method.
The last method is to directly punch holes in the welding plate, with minimal parasitic inductance. However, problems may occur in welding, and whether to use it depends on the processing ability and mode. The third and fourth methods are recommended.
It is important to note that some engineers, in order to save space, sometimes allow multiple capacitors to pass through a common hole, which should not be done under any circumstances. It is better to optimize the design of capacitor combination and reduce the number of capacitors.